1. Technical Field of the Invention
This invention pertains to circuit chip powering. More specifically, it relates to providing to individual functional units a selectable power supply, thereby increasing processing speed while reducing power consumption.
2. Background Art
Computers are becoming faster with each passing development cycle. Much of this increase in speed is due to ever smaller component and interconnection technologies used in manufacturing the microprocessors. With transistor densities increasing by an estimated 50% per year, technology is expected to reach a point where it becomes prohibitively expensive to improve the size of a transistor.
The possibility of these technological limits will soon make it more and more difficult for computer designers to gain the yearly speedup necessary to perpetuate Moore""s law. Thus, in order to continue to achieve performance gains, new methods must be used to push computer design to new limits. One of these methods is asynchronous design.
An advantage of asynchronous logic in a microprocessor is its low power consumption when compared with similar synchronous logic. Asynchronous logic, operating in an unclocked domain, consumes much less power due to the fact that there are no logic transitions based on a clock. Consequently, the speed and power consumption of any piece of asynchronous logic will be dependent on the data and the voltage supplied to the logic gates.
A common method of improving the performance of asynchronous logic has been to increase the power supply voltage. This increased voltage makes logic gates function much more rapidly. Unfortunately, the power consumed in the transition of a circuit, which is due to a brief short circuit current, is proportional to the supply voltage. Thus, when asynchronous logic designers increase the speed of their chips by increasing the voltage of the power supply, they also increase the power needed to drive the logic. In most cases the asynchronous chip is powered by the same voltage source throughout. This source even supplies units that are executing functions that cannot be applied until after some critical function has completed, as would be the case of an in-order chip executing two instructions in parallel. This increased voltage supply throughout the chip executes the critical instruction more rapidly, but also causes other units executing non-critical instructions to use more power, thus dissipating more heat and draining batteries faster.
As an example of this problem, consider the case of an asynchronous fixed point unit with the ability to execute multiply and add instructions simultaneously. An instruction pipeline would typically have a multiply instruction in the execute stage and an add instruction in the decode stage simultaneously. It would execute the multiply instruction, while adding any referenced registers to its list of dependencies. Shortly afterward it might find that the add instruction used no registers with data dependency. It would then use the adder in the fixed point unit to execute the add instruction. An in-order chip would most likely wait for the multiply instruction to complete, update the appropriate registers, then update registers for the add instruction. If the add instruction took less time than the multiply instruction, then the adder would be held until its results could be applied to the machine registers, doing no useful work while it is being held. If the adder were to use the same power supply as the multiplier in this example, the speed advantage gained by the adder from the extra voltage would be useless since the adder is held from completion until after the divide instruction is finished. If the adder were to be given a lower supply voltage during the execution of the add instruction than that given to the multiplier, the adder would save a considerable amount of power without effecting the overall performance of the chip.
It is an object of the invention to provide an improved system and method of chip powering.
It is a further object of the invention to provide an improved system and method of chip powering which increases processing speed while reducing power consumption.
It is a further object of the invention to provide an improved system and method of chip powering where individual execution units are provided selectable power to increase processing speed in critical units while reducing power in less critical units without delaying completion of processing in the critical units.
In accordance with the invention, a system and method is provided for selectively powering execution units from a plurality of power sources, the power to each execution unit being selected based upon expected time to completion of processing within the execution unit.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.